The need for memory address decoding arises from the fact that the main memory of a computer system is not constructed from a single component, which uniquely addresses each possible memory location.
Imagine a situation where two 1M memory chips are connected to a 32-bit address bus to make 2M of memory available. Each memory chip will need twenty address lines to uniquely identify each location in it. If the address lines of each memory chip were simply connected to the first twenty CPU address lines, then both memory chips would be accessed simultaneously whenever the CPU referred to any address. There are several memory addressing schemes that address this problem.
This is the simplest and least expensive form of address decoding. In the above example, we could connect the chip select input of one memory chip to the last CPU address line, and the chip select input of the other to the same address line but via an inverter. In this way the two chips would never be accessed simultaneously.
However, this is very inefficient. Eleven of the address lines are not used, and one of the two memory chips is always selected. The usable address space of the computer has been reduced from 4G to 2K. Partial address decoding is used in small dedicated systems where low cost is the most important factor. The penalty paid is that not all the address space can be used, and future expansion will be difficult.
Full address decoding is when each addressable location within a memory component corresponds to a single address on the CPU's address bus. That is, every address line is used to specify each physical memory location, through a combination of specifying a device and a location within it.
Full address decoding is very efficient in the use of the available address space, but is often impracticable to use because of the excessive hardware needed to implement it. This is particularly true where devices with a small number of addressable locations (for example memory-mapped I/O devices) are used.
Block address decoding is the merger of partial address decoding and full address decoding. The memory space is divided into a number of blocks. For example, in a system with a 32-bit address bus, the memory space could be divided into 4096 blocks of 1M. This could be implemented using simple decoding devices.
Many real systems employ a combination of the above decoding techniques. For example, several small devices may reside in the same block by using partial address decoding within that block.
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