The VHDL Requirement
1. VHDL is a language
for design and description of hardware. Usable for design documentation, high-level
description, simulation, synthesis and testing of the hardware.
2. Support for Design
Hierarchy. Design consists of an interface description and separate part(s) for
describing its operation.
3. Library Support.
This is for design management, for user and system defined primitives. The
libraries should be accessible to other designers.
4. Support for
Concurrent and Sequential Statements.
5. Configurable
Generic Design.
6. Type Declaration
and Usage. Not limited to bits or Boolean types. Supports array, integer etc
with a strong type checking.
7. Use of
Subprograms. Ability to define and use functions and procedures.
8. Timing Control.
Ability to specify timing at all levels.
9. Structural
Specification. Constructs for specifying structural decomposition of hardware
at all levels.
The previous section is The VHDL Introduction and Background.
The next section is The VHDL Template.
Created for MS EcE, VHDL part of the Course – ECCE Department 2005