A more common strategy is to use interrupt driven I/O. This strategy allows the CPU to carry on with its other operations until the module is ready to transfer data. When the CPU wants to communicate with a device, it issues an instruction to the appropriate I/O module, and then continues with other operations. When the device is ready, it will interrupt the CPU. The CPU can then carry out the data transfer as before.
This also removes the need for the CPU to continually poll input devices to see if it must read any data. When an input device has data, then the appropriate I/O module can interrupt the CPU to request a data transfer.
An I/O module interrupts the CPU simply by activating a control line in the control bus. The sequence of events is as follows.
1. The I/O module interrupts the CPU.
2. The CPU finishes executing the current instruction.
3. The CPU acknowledges the interrupt.
4. The CPU saves its current state.
5. The CPU jumps to a sequence of instructions, which will handle the interrupt.
The situation is somewhat complicated by the fact that most computer systems will have several peripherals connected to them. This means the computer must be able to detect which device an interrupt comes from, and to decide which interrupt to handle if several occur simultaneously. This decision is usually based on interrupt priority. Some devices will require response from the CPU more quickly than others; for example, an interrupt from a disk drive must be handled more quickly than an interrupt from a keyboard.
Many systems use multiple interrupt lines. This allows a quick way to assign priorities to different devices, as the interrupt lines can have different priorities. However, it is likely that there will be more devices than interrupt lines, so some other method must be used to determine which device an interrupt comes from.
Most systems use a system of vectored interrupts. When the CPU acknowledges an interrupt, the relevant device places a word of data (a vector) on the data bus. The vector identifies the device, which requires attention, and is used by the CPU to look up the address of the appropriate interrupt handing routine.