Memory Management: Speed

The speed of memory components and modules is one of the most important factors in optimizing a memory configuration. In fact, all computer systems specify a memory component speed. Ensuring memory compatibility requires conforming to this specification. There are three measurements of memory component and module speed: access time, megahertz, and bytes per second.

ACCESS TIME

Prior to SDRAM, memory speed was expressed by access time, measured in nanoseconds (ns). A memory's access time indicates the amount of time it takes to deliver a data requested. So, smaller numbers indicate faster access times. Typical speeds were 80ns, 70ns, and 60ns.

MEGAHERTZ

Beginning with the development of SDRAM technology, memory module speed has been measured in megahertz (MHz). Speed markings on the memory chips them-selves are typically still in nanoseconds. This can be confusing, especially since these nanosecond markings no longer measure access time, but instead measure the number of nanoseconds between clock cycles. For SDRAM chips with speeds of 66MHz, 100MHz, and 133MHz, for example, the corresponding marking on the chips are -15, -10, and -8, respectively.

This table shows the method for determining speed equivalencies between MHz and ns ratings.

The speed of memory is limited by the speed of the memory bus, which is the slowest link in the process.

BYTES PER SECOND

Converting MHz to bytes per second can be confusing at first. The two most important pieces of information you need to make the conversion is the speed (in MHz) and the width (in bits) of the bus.

Bus Width: If you have an 8-bit bus, then 8 bits, or 1 byte of information at a time can travel on the bus. If you have a 64-bit bus, then 64-bits, or 8 bytes of information can travel at a time.

Bus Speed: If the memory bus speed is 100MHz, this measures 100 million clock cycles per second. Typically, one packet of information can travel on each clock cycle. If the 100MHz bus is 1 byte wide, then data can travel at 100 megabytes per second. Data travels on a 100MHz, 64-bit bus at 800 megabytes per second.

Special Topic: Refresh Rates

Refresh is the process of recharging, or re-energizing, the "memory cells" in a memory chip. Internally, computer memory is arranged as a matrix of memory cells in rows and columns - like the squares on a checkerboard - with each column being further divided by the I/O width of the memory chip. The entire organization of rows and columns is called a DRAM array. DRAM is called "dynamic" RAM because it must be refreshed, or re-energized, thousands of times each second in order to retain data. It has to be refreshed because its memory cells are designed around tiny capacitors that store electrical charges. These capacitors work like very tiny batteries that lose their stored charges if they are not re-energized. Also, the process of reading data from the memory array drains these charges, so the memory cells must also be pre-charged before reading the data.

Cells are refreshed one row at a time (usually one row per refresh cycle). The term refresh rate refers not to the time it takes to refresh the memory but to the total number of rows that it takes to refresh the entire DRAM array. For example, a refresh rate of 2K indicates that it takes 2,048 rows to refresh the array; likewise, a 4K rate indicates 4,096 rows.

Normally, the system's memory controller initiates the refresh operation. But some chips are able to "self refresh." This means that the DRAM chip has its own refresh circuitry and does not require intervention from the CPU or external memory controller. Self-refresh modules dramatically reduce power consumption and are often used in portable computers.

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